This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to the structure of a contact area between a thin film conductive film and a metal wiring layer and a method for manufacturing the same and can be applied to a nonvolatile semiconductor memory and a method for manufacturing the same, for example.
Recently, it is strongly required to enhance the operation speed and integration density of semiconductor devices, and in order to meet the requirement, the size of the device tends to be reduced with the power source voltage kept unchanged. In other words, since the electric field in the device keeps increasing, the thickness of the gate oxide film cannot be reduced, particularly, in a nonvolatile semiconductor memory, since a high voltage is applied in the writing/erasing operation, the withstanding voltage of the gate oxide film becomes a problem.
Therefore, in the conventional nonvolatile semiconductor memory, a plurality of gate oxide films are used, thick gate oxide films are used for elements (which are hereinafter referred to as HV elements) to which a high power source voltage is applied, and gate oxide films which are thinner than the above thick gate oxide films are used for other elements (which are hereinafter referred to as LV elements, for example, nonvolatile memory cells) which are operated on a voltage lower than the above power source voltage.
On the other hand, in a case where a plurality of voltages are required in the device, devices having a plurality of external power sources are widely and frequently used. In such a device, a resistance type source voltage dividing system using high-resistance elements is often used in order to selectively divide a plurality of external power source voltages into a plurality of power source voltages in the device.
A method using a polysilicon film for the floating gate of a nonvolatile memory cell as the high-resistance element in the nonvolatile memory is known in the art and the method is explained below with reference to FIGS. 1A to 3B.
First, as shown in FIG. 1A, an element isolation insulating film 302 is formed on a semiconductor substrate 301 and a gate oxide film 303 for HV element is formed on that portion of the semiconductor substrate 301 on which the element isolation insulating film 302 is not formed. Then, a polysilicon film 304 is formed and a resist pattern 305 is formed on the polysilicon film in a peripheral element forming area.
After this, portions of the polysilicon film 304 and silicon oxide film 303 which lie in an area other than the HV element forming area are selectively removed by etching with the resist pattern 305 used as a mask and then the resist pattern 305 is removed.
Next, as shown in FIG. 1B, after a silicon oxide film 306 used for LV element is formed, a polysilicon film 307 is formed and a resist pattern 308 is formed on the polysilicon film in an LV element (cell and high-resistance element) forming area.
Then, portions of the polysilicon film 307 and silicon oxide film 306 which lie in an area other than the LV element (cell and high-resistance element) forming area are selectively removed by etching with the resist pattern 308 used as a mask and then the resist pattern 308 is removed.
Next, as shown in FIG. 1C, an SiO.sub.2 film 309 and a polysilicon film 310 are formed, for example, on the entire surface (not necessarily on the entire surface) of the polysilicon film 307 and polysilicon film 304 and then a resist pattern 311 is formed on the polysilicon film 310 in the LV element forming area.
Then, as shown in FIG. 2A, portions of the polysilicon film 310 and SiO.sub.2 film 309 are selectively removed by etching with the resist pattern 311 used as a mask and then the resist pattern 311 is removed.
Next, a WSi film 312 is formed on the entire surface (not necessarily on the entire surface) and a resist pattern 313 is formed on the WSi film in the HV element forming area and the cell forming area. After this, portions of the WSi film 312 and polysilicon films 310, 304 are selectively removed by etching with the resist pattern 313 used as a mask as shown in FIG. 2B.
Then, a resist pattern 314 is formed on a portion in an area other than the cell forming area without removing the resist pattern 313. After this, as shown in FIG. 2C, portions of the SiO.sub.2 film 309 and polysilicon film 307 are selectively removed by etching with the resist patterns 313, 314 used as a mask and then the resist patterns 313, 314 are removed. After this, a post-oxidation process is effected to form an SiO.sub.2 film 315 and then diffusion layers 316 of the cells and diffusion layers 317 of the peripheral elements are formed.
Next, as shown in FIG. 3A, an SiO.sub.2 film 318 is formed on the entire surface of the structure, a resist pattern 319 is formed on a portion in an area other than the contact areas and contact holes are formed by etching with the resist pattern 319 used as a mask.
After the resist pattern 319 is removed, aluminum wirings 320 are formed as shown in FIG. 3B.
It is desirable that a resistance element be formed with sufficiently high resistance and it is required to reduce the parasitic capacitance in order to attain a high-speed operation. In order to meet the above requirement, the film thickness of the polysilicon film used as the resistance element must be reduced. This also applies to the device explained before as the conventional device, and it becomes more desirable as the film thickness of the polysilicon film 307 which is partly used as the resistance element is reduced.
However, in the above-described conventional case, the contact holes shown in FIG. 3B may penetrate the polysilicon film 307 for the resistance element which is made sufficiently thin when the contact holes are formed by etching, and in the worst case, it becomes impossible to maintain insulation between the underlying substrate and the resistance element, thereby causing the manufacturing yield to be lowered.
Therefore, it is a common practice to form the polysilicon film 307 for the resistance element having a film thickness which is as large as approx. 200 nm even though the parasitic capacitance of the resistance element is increased and this imposes a limitation on the high-speed operation of the device.
Further, even if the film thickness of the polysilicon film 307 for the resistance element is increased to some extent, penetration of the contact hole cannot be sufficiently prevented because of a fluctuation in the etching process, thereby causing the manufacturing yield to be lowered.